The present invention relates generally to power saving methodologies for memory such as cache systems. In some embodiments, it provides a cache organization with a non-intrusive power management interface.
Memory systems such as static random access memory (SRAM) cache using cells such as the so-called 6T, 4T, or other, typically have a minimum required Vcc when in operation. Due to factors (e.g., aging, di/dt voltage droop, IR drop, and process variation) that reduce how much voltage the memory system actually sees, a guardband (or error margin) is added to the specified minimum supply to account for worst case conditions. For example, with some processor cache, guardbands of up to 100 mV may be employed, i.e., added to the minimum required Vcc. Accordingly, solutions for reducing utilized guardbands may be desired.